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CS5651
CS5651
High Performance Dual Channel Current Mode Controller with ENABLE
Description
The CS5651 is a high performance, fixed frequency, dual current mode controller specifically designed for Off-Line and DC to DC converter applications. It offers the designer a cost effective solution with minimal external components. This integrated circuit features a unique oscillator for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, and two high current totem pole outputs ideally suited for driving power MOSFETs. One of the outputs, VOUT2 is switchable via the ENABLE2 pin. Also included are protective features consisting of input and reference undervoltage lockouts, each with hysteresis; cycle-by-cycle current limiting; and a latch for single pulse metering of each output. The CS5651 is pin compatible with the MC34065H.
Features
s Oscillator has Precise Duty Cycle Limit and Frequency Control s 500kHz Current Mode Operation s Automatic Feed Forward Compensation s Separate Latching PWMs for Cycle-By-Cycle Current Limiting s Internally Trimmed Reference with Undervoltage Lockout s Switchable Second Output s Two High Current Totem Pole Outputs s Input Undervoltage Lockout with Hysteresis
Block Diagram
VCC
VREF
5.0V Ref
VCC Undervoltage Lockout
VREF Undervoltage Lockout
SYNC CT RT Latching PWM 1 Oscillator
VOUT1
+
Sense1
Package Options
16L PDIP & SO Wide
VFB1
-
Error Amp 1 COMP1 ENABLE2 Latching PWM 2 VOUT2
SYNC 1 CT 2 RT 3
16 15 14 13 12 11 10 9
VCC VREF ENABLE2 VFB2 COMP2 Sense2 VOUT2 Pwr Gnd
VFB2
+ -
Error Amp 2 COMP2
Sense2
VFB1 4 COMP1 5 SENSE1 6 VOUT1 7
Gnd
Pwr Gnd
Gnd 8
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 3/9/99
1
A
(R)
Company
CS5651
Absolute Maximum Ratings Output Current, Source or Sink (Note 1) ......................................................................................................................400mA Output Energy (capacitive load per cycle) .......................................................................................................................5.0J Current Sense, Enable and Voltage ......................................................................................................................-0.3 to +5.5V Feedback Inputs Sync Input High State (Voltage).............................................................................................................................................5.5V Low State (Reverse Current)..........................................................................................................................-5.0mA Error Amp Output Sink Current......................................................................................................................................10mA Storage Temperature Range ................................................................................................................................-65 to +150C Operating Junction Temperature...................................................................................................................................+150C Lead Temperature Soldering Wave Solder (through hole styles only)..........................................................................10 sec. max, 260C peak Reflow (SMD styles only)...........................................................................60 sec. max above 183C, 230C peak
Electrical Characteristics: VCC = 15V, RT = 8.2k, CT = 3.3nF, 0C TA 70C [Note 2], unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Reference Section Reference Output Voltage, VREF Line Regulation Load Regulation Total Output Variation over Line, Load and Temperature Output Short Circuit Current s Oscillator and PWM Sections Total Frequency Variation 11V VCC 15V, Tlow TA Thigh over Line and Temperature Frequency Change with Voltage Duty Cycle at each Output SYNC Current 11V VCC 15V Maximum High State VIN = 2.4V Low State VIN = 0.8V 46.0 46.5 49.0 0.2 49.5 170 80 51.5 1.0 52.0 250 160 kHz % % A IOUT = 1.0mA, TJ = 25C 11V VCC 15V 1.0mA IOUT 10mA 4.85 30 100 4.9 5.0 2.0 3.0 5.1 20.0 25.0 5.15 V mV mV V mA
s Error Amplifiers Voltage Feedback Input Input Bias Current Open-Loop Voltage Gain Unity Gain Bandwidth Output Current Output Voltage Swing VOUT = 2.5V VFB = 5.0V 2.0V VOUT 4.0V TJ = 25C (Note 5) Source VOUT = 3.0V, VFB = 2.3V Sink VOUT = 1.2V, VFB = 2.7V High State RL = 15k to ground, VFB = 2.3V Low State RL = 15k to VREF, VFB = 2.7V 2 65 0.7 60 -0.45 2.00 5.0 2.42 2.50 -0.1 100 1.0 90 -1.00 12.00 6.2 0.8 1.1 2.58 -1.0 V A dB MHz dB mA mA V V
Power Supply Rejection Ratio VCC = 11V to 15V
CS5651
Electrical Characteristics: VCC = 15V, RT = 8.2k, CT = 3.3nF, 0C TA 70C [Note 2], unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s Current Sense Section Current Sense Input Voltage Gain Maximum Current Sense Input Threshold Input Bias Current Propagation Delay s Output 2 Enable Pin Enable Pin Voltage High State Low State Low State Input Current s Drive Outputs Output Voltage Low State High State Output Voltage with UVLO Activated Output Voltage Rise Time Output Voltage Fall Time ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA VCC = 6.0V, ISINK = 1.0mA CL = 1.0nF (Note 5) CL = 1.0nF (Note 5) 0.1 1.6 13.5 13.4 0.1 28 25 0.4 2.5 V V V V V ns ns ENABLE2 enabled ENABLE2 disabled VIL = 0V 3.5 0.0 100 250 VREF 1.5 400 V V V A Current Sense Input to Output (Note 5) (Notes 3 and 4) (Note 3) 2.75 0.9 3.00 1.0 -2.0 150 3.25 1.1 -30.0 300 V/V V A ns
13.0 12.0
1.1 150 150
s Undervoltage Lockout Section Start-Up Threshold Minimum Operating Voltage Hysteresis s Total Device Start-Up Current Operating Current VCC = 12V (Note 2) 0.6 20 1.0 25 mA mA 13 9.0 14 10.0 4.0 15 11.0 V V V
Note 1: Maximum package power dissipation limits must be observed. Note 2: Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Note 3: This parameter is measured at latch trip point with VFB = 0V.
Note 4: Comparator gain is defined as: AV=
V Compensation V Current Sense
Note 5: These parameters are guaranteed by design but not 100% tested in production.
3
CS5651
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
16 L PDIP & SO Wide 1 SYNC A positive going pulse applied to this input will synchronize the oscillator. A DC voltage within the range of 2.4V to 5.5V will inhibit the oscillator. Timing capacitor CT connects pin to ground setting oscillator frequency. Resistor RT connects to ground setting the charge current for CT. Its value must be between 4.0k and 16k. The inverting input of error amplifier 1. Normally it is connected to the switching power supply output. The output of error amplifier 1, for loop compensation. Output 1 pulse by pulse current limit. Drives the power switch at output 1. Logic ground Power ground. Power device return is connected to this pin. Drives the power switch at output 2. Output 2 pulse by pulse current limit. Output of error amplifier 2, for loop compensation. Inverting input of error amplifier 2. Normally it is connected to the switching power supply output. Output 2 disable. A logic low at this pin disables VOUT2. 5.0V reference output. It can source current in excess of 30mA. The positive supply of the IC. The minimum operating voltage range after start-up is 9V. Typical Performance Characteristics Timing Resistor vs. Oscillator Frequency
16 14
2.2n
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CT RT VFB1 COMP1 Sense1 VOUT1 Gnd Pwr Gnd VOUT2 Sense2 COMP2 VFB2 ENABLE2 VREF VCC
Max. Output Duty Cycle vs. Oscillator Frequency
50 MAXIMUM DUTY CYCLE (%) 48 46 44 42 40 38 10k VCC = 15V RT = 4.0k to 16k CL = 15pF TA = 25C 30k 50k 100k 300k 500k 1.0M
RT TIMING RESISTOR (K)
100p
1.0n F
500
220 pF
330
F
3.3
pF
12
10 CT= nF
pF
F
5.0 nF
nF
10 8.0
VCC= 6.0 15V 4.0 10k TA=25C 30k 50k 100k 300k 500k 1.0M f OSC OSCILLATOR FREQUENCY (Hz)
f OSC OSCILLATOR FREQUENCY (Hz)
Error Amp Open-Loop Gain & Phase vs. Frequency
AVOL, OPEN-LOOP VOLTAGE GAIN (dB) 100 80 60 40 20 0 -20 10k GAIN VCC = 15V VO = 1.5V TO 2.5V RL = 100k TA = 25C PHASE 0 30 60 90 120 150 180 10M Phase Margin (DEGREES)
Current Sense Input Threshold vs. Error Amp Output Voltage
1.2 Vth, CURRENT SENSE INPUT THRESHHOLD (V) VCC = 15V 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 ERROR AMP OUTPUT VOLTAGE (V) TA = 125C TA = 25C TA = -55C
100k
1.0k
10k
100k
1.0M
f, FREQUENCY (Hz)
4
CS5651
Typical Performance Characteristics: continued Reference Voltage Change vs. Source Current
0 VCC = 15V VREF, REFERENCE Voltage (mV) -4.0 -8.0 -12 -16 -20 -24 0 20 40 60 80 100 I ref, REFERENCE SOURCE CURRENT (mA) 120 TA = 125C TA = 25C
Reference Short Circuit Current vs. Temperature
ISC, REFERENCE SHORT CIRCUIT CURRENT (mA) 120
100
TA = -55C
80
60 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Output Saturation Voltage vs. Load Current
0
VCC
Supply Current vs. Supply Voltage
32 ICC, SUPPLY CURRENT (mA)
RT=8.2k CT=3.3nF VFB 1, 2=0V CURRENT SENSE 1, 2=0V TA=25C
SOURCE SATURATION (LOAD TO GROUND)
Vsat, OUTPUT SATURATION VOLTAGE (V)
-1.0 -2.0
VCC=15V 80S PULSED LOAD 120Hz RATE TA=25C
24
TA= -55C
16
2.0 1.0 0 0
TA= -55C TA=25C GND
8.0
SINK SATURATION (LOAD TO VCC)
0
200 400 600 OUTPUT LOAD CURRENT (mA)
800
0
4.0
8.0
12
16
20
VCC, SUPPLY VOLTAGE (V) - CS-5651
Operating Description The CS5651 is a high performance, fixed frequency, dual channel current mode PWM controller for Off-Line and DC to DC converter applications. Each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. The oscillator, reference, and undervoltage lockout circuits are common to both channels.
Oscillator
making this controller suitable for high frequency power conversion applications. In noise sensitive applications it may be necessary to synchronize the converter with an external system clock. This can be accomplished by applying an external clock signal. For reliable synchronization, the oscillator frequency should be set about 10% slower than the clock frequency. The rising edge of the clock signal applied to SYNC, terminates the charging of CT and VOUT2 conduction. By tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved.
Error Amplifier
The oscillator has both precise frequency and duty cycle control. The oscillator frequency is programmed by the timing components RT and CT. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink, that generates a symmetrical 50 percent duty cycle waveform at CT. The oscillator peak and valley thresholds are 3.5V and 1.6V respectively. The source/ sink current is controlled by resistor RT. For proper operation over temperature range RT's value should be between 4.0k to 16k. As CT charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower NOR gates high. This, in conjunction with a precise amount of delay time introduced into each channel, produces well defined non-overlapping output duty cycles. Output 2 is enabled while CT is charging, and Output 1 is enabled during the discharge. Even at 500kHz, each output is capable of approximately 44% duty cycle, 5
Each channel contains a fully-compensated error amplifier with access to the output and inverting input. The amplifier features a typical dc voltage gain of 100 dB, and a unity gain bandwidth of 1.0 MHz with 71 degrees of phase margin. The non-inverting input is internally biased at 2.5V. The converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. The maximum input bias current is -1.0 A which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider resistance. Its output voltage is offset by two diode drops (1.4V) and divided by three before it connects to the inverting input of the current sense comparator. This guarantees that both
CS5651
Operating Description: continued outputs are disabled when the error amplifier output is at its lowest state (VOUT(LOW)). This occurs when the power supply is operating at light or no-load conditions, or at the beginning of a soft-start interval. The minimum allowable error amplifier feedback resistance is limited by the amplifier's source current capability (0.5 mA) and the output voltage (VOUT(High)) required to reach the current sense comparator 1.0V clamp level with the error amplifier inverting input at ground. This condition happens during initial system start up or when the sensed output is shorted: RF(min) (3 x 1.0V) + 1.4V = 8.8k 0.5mA comparator has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 14V and 10V for the CS5651. The VREF comparator disables the outputs until the internal circuitry is functional. This comparator has upper and lower thresholds of 3.6V and 3.4V. The guaranteed minimum operating voltage after turn-on is 11V for CS5651. Outputs and Power Ground Each channel contains a single totem-pole output stage specifically designed for driving a power MOSFET. The outputs have up to 1.0A peak current capability and have a typical rise and fall time of 28ns with a 1.0nF load. Internal circuitry has been added to keep the outputs in active pull-down mode whenever undervoltage lockout is active. An external pull-down resistor is not needed. Cross-conduction current in the totem-pole output stage has been minimized for high speed operation. The average added power due to cross-conduction with VCC = 15V is only 60mW at 500kHz. Although the outputs were optimized for MOSFET's, they can easily supply the negative base current required by bipolar NPN transistors for enhanced turn-off. Because the outputs do not contain internal current limiting circuitry, an external series resistor may be required to prevent the peak output current from exceeding the 1.0A maximum rating. The sink saturation voltage (VOL) is less than 0.4V at 100mA. A separate Power Ground pin is provided and will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly important when the Ipk(max) clamp level is reduced. This input is used to switch VOUT2. VOUT1 can be used to control circuitry that runs continuously; e.g. volatile memENABLE2 ory, the system clock, or a remote controlled receiver. The VOUT2 output can control the high power circuitry that can be turned off when not needed.
Current Sense Comparator and PWM Latch The CS5651 operates as a current mode controller. Output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output. The error signal controls the peak inductor current on a cycleby-cycle basis. The current sense comparator-PWM Latch combination ensures that only a single pulse appears at the output during any given oscillator cycle. The current is converted to a voltage by connecting sense resistor RSense in series with the source of output switch Q1 and ground. This voltage is monitored via the Sense1,2 pins and compared to a voltage derived from the error amp output. The peak current under normal operating conditions is controlled by the voltage at COMP where: Ipk = VCOMP - 1.4V 3RSense
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage is too high. Under these conditions, the current sense comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch current is: Ipk(max) = 1.0V RSense
Voltage Reference The 5.0V bandgap reference is trimmed to 2.0% tolerance. The reference has short circuit protection and is capable of sourcing 30mA for powering any additional external circuitry. Design Considerations High frequency circuit layout techniques are imperative to prevent pulse-width jitter. This is usually caused by excessive noise pick-up imposed on the current sense or voltage feed-back inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit board layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input fil6
Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. The addition of an RC filter on the current sense input reduces this spike to an acceptable level. Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stages are enabled. VCC and the reference output VREF are monitored by separate comparators. Each
CS5651
Operating Description: continued ter capacitor. Ceramic bypass capacitors (0.1F) connected directly to VCC and VREF may be required to improve noise filtering. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs. The error amp compensation circuitry and the converter output voltage-divider should be located close to the IC and as far as possible from the power switch and other noise generating components.
Timing Diagram
SYNC Capacitor CT Latch 1 "Set" Input COMP1 Sense1 Latch 1 "Reset" Input VOUT1
ENABLE2 0V Latch 2 "Set" Input COMP2 Sense2 Latch 2 "Reset" Input VOUT2
Typical Application Diagram
Dual Boost Regulator
VCC CF1 +
VIN
5.0V CF2 VREF 2.5V R Sync VOUT1 RFB1 RFB2 VFB1 COMP1 ENABLE2 VOUT2 RFB3 RFB4 VFB2 COMP2 + Error Amp 2 + Error Amp 1 + Oscillator Current Sense 2R Comparator 1 + 1.0VREF R + 1.0V R Internal Bias + 3.4V 20k
Reference Regulator
+ -
+ VCC + UVLO 14V L1 D1 + Q1 L2 VOUT1 COUT1
VREF UVLO
RT
CT
PWM Latch 1 S RQ
VOUT1 RSense1 Sense1 Q2 D2 + VOUT2 COUT2
250A + Current Sense Comparator 2 2R + 1.0mA R 1.0V PWM Latch 2 S RQ R
VOUT2
Sense2
RSense2
Gnd
Pwr Gnd
7
CS5651
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
Lead Count 16 Lead PDIP 16 Lead SO Wide
Metric Max Min 19.69 18.67 10.50 10.10
D English Max Min .775 .735 .413 .398
Thermal Data RJC RJA typ typ
16 Lead PDIP 42 80
16 Lead SO Wide 23 105
C/W C/W
Plastic DIP (N); 300 mil wide
7.11 (.280) 6.10 (.240)
8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115)
1.77 (.070) 1.14 (.045)
2.54 (.100) BSC
.356 (.014) .203 (.008)
0.39 (.015) MIN. .558 (.022) .356 (.014) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same.
REF: JEDEC MS-001
D
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299) 7.40 (.291)
10.65 (.419) 10.00 (.394)
0.51 (.020) 0.33 (.013)
1.27 (.050) BSC
2.49 (.098) 2.24 (.088)
2.65 (.104) 2.35 (.093)
1.27 (.050) 0.40 (.016)
REF: JEDEC MS-013
0.32 (.013) 0.23 (.009) D 0.30 (.012) 0.10 (.004)
Ordering Information
Part Number CS5651GN16 CS5651GDW16 CS5651GDWR16
Rev. 3/9/99
Description 16L PDIP 16L SO Wide 16L SO Wide (Tape & Reel) 8
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
(c) 1999 Cherry Semiconductor Corporation

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